1. Field of the Invention
This invention pertains in general to a semiconductor device, and, more particularly, to a substrate-biased silicon diode and a method for making the same.
2. Description of the Related Art
A semiconductor integrated circuit (IC) is generally susceptible an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC. The high current may be built-up from a variety of sources, such as the human body. Many schemes have been implemented to protect an IC from an ESD event. A common protection scheme is using a parasitic transistor associated with an n-type metal-oxide semiconductor (MOS) with the source coupled to ground and the drain connected to the pin to be protected from an ESD event.
Diodes or diode-coupled transistors have been used for ESD protection in radio-frequency (RF) applications. In a RF IC, an on-chip ESD circuit should ideally provide robust ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency. In deep-submicron complementary metal-oxide semiconductor (CMOS) process technology with shallow-trench isolations (STIs), a diode has been used for ESD protection and is generally formed contiguous with either an N+ or P+ diffusion region in a semiconductor substrate. FIG. 1A shows a cross-sectional view of a known diode ESD protection structure formed in an IC. Referring to FIG. 1A, a P+ diffusion region is bound by STIs on either side, and therefore the diode formed by the STI is also known as an STI-bound diode. The STI-bound diode exhibits a bottom capacitance, Cbottom. However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P+ diffusion region and the STIs around the P+ region.
FIG. 1B shows a cross-sectional view of another known diode ESD protection structure, known as a polysilicon-bound diode, introduced to address the leakage current problem with an STI-bound diode. The P+ diffusion region in a polysilicon-bound diode is now defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated. However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the addition of the sidewall junction capacitance of the P+ diffusion region.
FIG. 2 is a circuit diagram showing a known ESD protection scheme using dual diodes. Referring to FIG. 2, the combination of the dual-diode structures and VDD-to-VSS ESD clamp circuit provides a path for an ESD current 2 to discharge, instead of through the internal circuits. When ESD current 2 is provided to signal a pad PAD1, and with a signal pad PAD2 relatively grounded, ESD current 2 is conducted to VDD through Dp1. ESD current 2 is discharged to VSS through the VDD-to-VSS ESD clamp circuit and flows out of the IC from Dn2 to PAD2. Diode Dp1 has a capacitance of Cp1 and diode Dn1 has a capacitance of Cn1. The total input capacitance Cin of the circuit shown in FIG. 2 primarily comes from the parasitic junction capacitance of diodes, and is calculated as follows:
Cin=Cp1+Cn1
wherein Cp1 and Cn1 are parasitic junction capacitances of diodes Dp1 and Dn1, respectively.
FIG. 3 is plot showing the relationship between a pad voltage and parasitic input capacitance of the circuit shown in FIG. 2. Referring to FIG. 3, when the voltage on the pad increases, the parasitic junction capacitance of Dp1 increases and the parasitic junction capacitance of Dn1 decreases. Therefore, the total input parasitic capacitance Cin is nearly constant. This characteristic is important in RF applications. However, the total parasitic capacitance of a polysilicon-bound diode, as compared to an STI-bound diode, is increased because of the addition of a sidewall capacitance, Csidewall, as shown in FIG. 1B.
Accordingly, the present invention is directed to a substrate-biased silicon diode and a method for making the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit device that includes a semiconductor substrate, a well region formed inside the semiconductor substrate, a first isolation structure formed inside the well region, a second isolation structure formed inside the well region and spaced apart from the first isolation structure, a dielectric layer disposed over the well region, and a layer of silicon, formed over the dielectric layer, including a p-type portion, an n-type portion and a center portion disposed between the p-type and n-type portions, wherein the p-type portion overlaps the first isolation structure and the n-type portion overlaps the second isolation structure.
Also in accordance with the present invention, there is provided an integrated circuit device receiving signals from a signal pad that includes at least one substrate-biased silicon diode responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals.
In one aspect of the invention, each of the at least one substrate-biased silicon diode includes a p-type silicon portion, an n-type silicon portion and a center silicon portion disposed between and contiguous with the p-type and n-type silicon portions.
In another aspect of the invention, there additionally includes a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one substrate-biased silicon diode.
Further in accordance with the present invention, there is provided an integrated circuit device receiving signals from a signal pad that includes a first plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the first plurality of substrate-biased silicon diodes including a p-portion and an n-portion, a second plurality of serially coupled substrate-biased silicon diodes responsive to the signals from the signal pad for providing electrostatic discharge protection from the signals, each of the second plurality of substrate-biased silicon diodes including a p-portion and an n-portion, and a detection circuit for detecting signals from the signal pad and providing a bias voltage to the first and second plurality of substrate-biased silicon diodes, wherein the signal pad is coupled to the p-portion of one of the first plurality of substrate-biased silicon diodes and the n-portion of one of the second plurality of the substrate-biased silicon diodes.
Additionally in accordance with the present invention, there is provided an integrated circuit device that comprises a semiconductor substrate, an insulator layer disposed over the semiconductor substrate, a silicon layer disposed over the insulator layer, which includes a first isolation structure formed inside the silicon layer, and a second isolation structure formed inside the silicon layer and spaced apart from the first isolation structure, a dielectric layer disposed over the silicon layer, and a layer of silicon, disposed over the dielectric layer, which includes a p-type portion, an n-type portion and a center portion disposed between and contiguous with the p-type and n-type portions.
Further in accordance with the present invention, there is provided a silicon-on-insulator circuit device receiving signals from a signal pad that includes at least one base-biased silicon diode, responsive to the signals from the signal pad, for providing electrostatic discharge protection.
In one aspect of the invention, the silicon-on-insulator is biased to control the at least one base-biased silicon diode.
Additionally in accordance with the present invention, there is provided a method for protecting a silicon-on-insulator device from electrostatic discharge that includes the steps of providing a signal to the device through a silicon-on-insulator circuit, providing a base-biased silicon diode in the silicon-on-insulator circuit, and protecting the device from electrostatic discharge produced with the base-biased silicon diode.
Also in accordance with the present invention, there is provided a method for protecting a complementary metal-oxide semiconductor device from electrostatic discharge that includes the steps of providing a signal to the device through a complementary metal-oxide semiconductor circuit, providing a substrate-biased silicon diode in the complementary metal-oxide semiconductor circuit, and protecting the device from electrostatic discharge produced from the signal with the substrate-biased silicon diode.
Moreover in accordance with the present invention, there is provided a method for forming a silicon diode that includes the steps of A method for forming a silicon diode, comprising the steps of forming a first silicon layer, forming a first isolation structure and a second isolation structure inside the first silicon layer, the first isolation structure being spaced apart from the second isolation structure, forming a dielectric layer over the silicon layer, forming a second silicon layer over the dielectric layer, forming dielectric spacers contiguous with the second silicon layer, implanting a first impurity having a first concentration into a first portion and a second portion of the second silicon layer, the first portion being contiguous with the second portion and the second portion overlapping a region of the first silicon layer between the first isolation structure and the second isolation structure, implanting a first impurity having a second concentration into the first portion of the second silicon layer, wherein the second concentration is greater than the first concentration, and implanting a second impurity into a third portion of the second silicon layer, wherein the third portion is contiguous with the second portion.
In one aspect of the invention, the steps of implanting a first impurity having a first concentration and implanting a first impurity having a second concentration create a diffused region adjacent one of first and second field isolation structures.
Also in accordance with the present invention, there is provided a method for forming a base-biased silicon diode that includes the steps of forming a first and second isolation structures inside a silicon layer, defining a base region inside the silicon layer, the base region being disposed between and contiguous with the first and second isolation structures, forming a dielectric layer over the well region, forming a layer of silicon over the dielectric layer, implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and the second portion overlapping a region of the silicon layer between the first isolation structure and the second isolation structure, implanting a first impurity having a second concentration into the first portion and second portion of the silicon layer, wherein the second concentration is greater than the first concentration, and implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure.
Further in accordance with the present invention, there is provided a method for forming a substrate-biased silicon diode that includes the steps of forming a first isolation structure and a second isolation structure spaced apart from the first isolation structure inside a silicon layer, forming a dielectric layer over the silicon layer, forming a layer of silicon having two ends over the dielectric layer, forming dielectric spacers contiguous with the two ends of the silicon layer, implanting a first impurity having a first concentration into a first portion and a second portion of the silicon layer, wherein the first portion is contiguous with the second portion and overlaps the first isolation structure, implanting a second impurity into a third portion of the silicon layer, wherein the third portion is contiguous with the second portion and overlaps the second isolation structure, and implanting a first impurity having a second concentration into the first portion of the silicon layer, wherein the second concentration is greater than the first concentration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide farther explanation of the invention as claimed.